INFORMAZIONI SU

Methodology of Logic Synthesis (the English translation of "Metodologie della sintesi logica")

Methodology of Logic Synthesis (traduzione in inglese del programma di Metodologie della sintesi logica) - cdl in Ingegneria Elettronica

Teacher

prof. aggr. Mirko LOGHI

Credits

6 CFU

Language

Italian

Objectives

The course illustrates the principle methods of analysing and summarizing the combinational and sequential circuits.

Acquired skills

- Terminology and mathematical theory used to model digital logic.
- Main logic families used in digital electronic systems.
- Analysis of functional and time behavior of combinational and sequential circuits.
- Development and optimization of combinational circuits.
- Digital arithmetic circuits.
- Development and optimization of finite state machines.

Lectures and exercises (topics and specific content)

Introduction to modern logic design (2 hours).
Boolean algebra: Boolean variables and functions; Hamming distance; Gray cod; error detecting and error correcting codes; function synthesis from truth table; glitches; digital circuits with a single operator (6 hours).
Two- and multi-level minimization: Karnough Maps; Quine-McCluskey algorithm (4 hours).
Algebraic and boolean transformations: algebraic rules. DC set: CDC set and ODC set(4 hours).
Logic families: CMOS; pass-transistor logic; NMOS; Dynamic logic; DCVLS (6 hours).
Basic combinational circuits: decoder; multiplexer; shifter (2 hours).
Arithmetic circuits: adder: subtractor; multiplier; divider (8 hours).
Delay in combinational circuits: critical path; static timing analysis (2 hours).
Latch and flip-flops: asynchronous SR latch; synchronous SR latch. Flip-flop: SR, JK, D, T; time behavior of flip-flops; registers; counters (6 hours).
Finite state machines: definitions; state transition table. State transition graph; state encoding; implementation; timing; clock-skew; metastability (8 hours).
Minimization of finite state machines: minimization of fully specified machines; minimization of incompletely specified machines (6 hours).
Development of finite state machines (6 hours). 
Exercises (6 hours).

References

- R. H. Katz, "Contemporary Logic Design", Addison Wesley
- Fummi, Sami, Silvano, "Progettazione digitale", McGraw-Hill

Type of exam

Written

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